1. Technical Field
This disclosure relates to solid state memory devices that use voltage reference values to determine the states of memory cells. More particularly, the disclosure relates to processes for selecting voltage reference values to use for performing memory read operations.
2. Description of the Related Art
Flash memory devices store information in an array of memory cells constructed with floating gate transistors. In single-level cell (SLC) flash devices, each cell stores a single bit of information. In multi-level cell (MLC) devices, each cell stores two or more bits of information. When a read operation is performed, the electrical charge levels of the cells are compared to one or more voltage reference values (also called “voltage thresholds” or “threshold levels”) to determine the state of each cell. In SLC devices, each cell is read using a single voltage reference value. In MLC devices, each cell is read using multiple voltage references values. Some flash devices implement commands for enabling an external memory controller to set the voltage reference values.
Various factors can contribute to data read errors in flash memory devices. These factors include charge loss or leakage over time, and device wear caused by usage. When the number of bit errors on a read operation exceeds the ECC (error correction code) correction capability of the storage subsystem, the read operation fails.
One known method for attempting to recover the data in this situation is to retry the memory read operation one or more times using adjusted voltage reference values. This process, sometimes called heroic error recovery, causes significant read latency to the host, and can cause the storage subsystem to fall below its performance specifications. As a result, heroic error recovery is generally not a useful process for extending the endurance of the storage subsystem